1. Field of the Invention
The present invention relates to a bus control device, and in particular, to a bus control device for effecting control such that particular resources are occupied for exclusive accesses.
2. Description of Related Art
In a multiprocessor system, a processor may exclusively access a particular resource such as an I/O device. In this case, to prohibit the other processors from accessing this particular resource, a corresponding lock variable (also referred to as a xe2x80x9clock wordxe2x80x9d) is locked; the lock variable is unlocked after an exclusive access has been completed.
Referring to FIG. 8, when a processor A reads out a lock variable corresponding to an I/O device which it is to access (step S801), and judges that the lock variable is unlocked (step S802), it locks the variable (step S803) Subsequently, the processor A accesses this I/O device (step S804), and after completing the final access (step S805), it unlocks the variable again (step S806).
On the other hand, if a processor B attempts to access the same I/O device, it first reads out the lock variable (step S811), but if the variable is already locked by the processor A, it waits for the variable to be unlocked. When the processor A unlocks the variable (step S806), the processor B then locks the variable (step S813). Subsequently, the processor B accesses this I/O device (step S814), and after completing the final access (step S815), it unlocks the variable again (step S816). In this manner, the lock function ensures exclusive accesses to resources such as I/O devices.
With the above described conventional technique, however, if a lock variable is present in a cache memory, a change in lock variable is completed between the processor and the cache memory. This operation is fast, but since I/O accesses are uncachable, that is, these accesses are made via a system bus without the use of the cache memory, the lock operation and the I/O access may be mutually reversed as described below. The cachable access using the cache memory and the uncachable access without the use of the cache memory are mutually separated using, for example, the attribute of each page or specifications in fields in the request.
Referring to FIG. 9, the final I/O access (901), which was issued by the processor A and then transferred to a bus control device A (902), has not been issued to a system bus 400. Due to the issue completion of the final I/O access, the processor A unlocks the lock variable, but the lock variable is actually present in its own cache memory. Therefore, the lock variable is accessed by accessing the cache memory (909). On the other hand, when the processor B requests the lock variable to be read out (911), a bus control device B issues this request to the system bus 400 (912) Since this read-out request hits the cache memory of the processor A, the bus control device A issues a read-out request to the processor A (913), which then returns read-out data including the lock variable to the system bus 400 via the bus control device A (914). A path used by the bus control device A to issue the I/O access to the system bus 400 differs from a path used by the same to return the read-out data to the system bus 400, so that the read-out data including the lock variable may be returned to the system bus before the above I/O access is issued to the system bus. The data including the lock variable is returned to the processor B via the bus control device B (915), thereby allowing the processor B to confirm that the lock variable is unlocked. After locking the lock variable (916), the processor B issues the first I/O access to the processor B (921), and the bus control device B issues the first I/O access of the processor B to the system bus 400 (922). Subsequently, when the bus control device A issues the I/O access of the processor A (902) to the system bus 400, the previously executed I/O access is temporally overtaken by the subsequently executed I/O access. If the previously executed I/O access is a write access and the subsequently executed I/O access is a read access, then old data, which is not updated by the previously executed I/O write access, is read out, resulting in data inconsistency.
It is an object of the present invention to solve the above-described problem to ensure exclusive accesses to particular resources.
A bus control device according to the present invention operates when a predetermined read-out request is issued on a bus, to command the read-out request to be retried if a predetermined write from a higher device has not been completed.
In addition, the bus control device according to the present invention is connected between a higher device and a bus, and includes a request buffer that holds a request issued from the higher device, and a retry control circuit operating when a predetermined read-out request is issued on the bus, to command the read-out request to be retried if the request held in the request buffer has been obtained through a predetermined write.
Additionally, an information processing system according to the present invention includes a higher device, a bus, and a bus control device connected between the higher device and the bus, wherein the bus control device includes a request buffer that holds a request issued from the higher device and a retry control circuit operating when a predetermined read-out request is issued on the bus, to command the read-out request to be retried if the request held in the request buffer has been obtained through a predetermined write.